Performing many operations simultaneously in Verilog -

in verilog, there easy way specify perform large number of operations @ once? example, verilog module below iterates simple function ten times on input, in single clock cycle.

module test (val_in,val_out);     input [15:0] val_in;     output [15:0] val_out;     wire [15:0] vals[10:1];     integer i;      assign vals[1]=val_in*val_in+val_in;     assign vals[2]=vals[1]*vals[1]+val_in;     assign vals[3]=vals[2]*vals[2]+val_in;     assign vals[4]=vals[3]*vals[3]+val_in;     assign vals[5]=vals[4]*vals[4]+val_in;     assign vals[6]=vals[5]*vals[5]+val_in;     assign vals[7]=vals[6]*vals[6]+val_in;     assign vals[8]=vals[7]*vals[7]+val_in;     assign vals[9]=vals[8]*vals[8]+val_in;     assign vals[10]=vals[9]*vals[9]+val_in;     assign val_out=vals[10]; endmodule // test 

is there way without specifying each iteration individually? know 1 create loop , store value @ each iteration, different above, not able run in single clock cycle.

sorry if naive question; i'm new verilog.

loop can created variables follows pattern, others keep is, here vals[1] , val_out seems have different pattern isolating these loop

module test (val_in,val_out);     input          [15:0] val_in;     output         [15:0] val_out;             wire   [15:0] vals[10:1];      assign vals[1]=val_in*val_in+val_in;      genvar i;     generate       for(i=2; i<=10; i=i+1) begin : grouped_vals        assign vals[i]=vals[i-1]*vals[i-1]+val_in;       end     endgenerate      assign val_out=vals[10];   endmodule