components - VHDL OR logic with 32 bit vector - 


zero <= result_i(31) or result_i(30) or result_i(29) or result_i(28)         or result_i(27) or result_i(26) or result_i(25) or result_i(24)         or result_i(23) or result_i(22) or result_i(21) or result_i(20)         or result_i(19) or result_i(18) or result_i(17) or result_i(16)         or result_i(15) or result_i(14) or result_i(13) or result_i(12)         or result_i(11) or result_i(10) or result_i(9) or result_i(8)         or result_i(7) or result_i(6) or result_i(5) or result_i(4)         or result_i(3) or result_i(2) or result_i(1) or result_i(0);

how can make shorter?

i assuming using std_logic/std_logic_vector types. can use or_reduce ieee.std_logic_misc. 

library ieee; use ieee.std_logic_misc.or_reduce; ... 0 <= or_reduce(result_i);

or write own function: 

function or_reduce(vector : std_logic_vector) return std_logic     variable result : std_logic := '0'; begin     in vector'range loop         result := result or vector(i);     end loop     return result; end function;

a general tip if starting out vhdl not forget functions , procedures. unlike verilog (without systemverilog) vhdl has support writing clean , high level code, synthesis, using functions , procedures. if doing repetitive sure sign should wrapped in function/procedure. in case there standard function ready used though.

you might want consider pipelining or-reduction , inserting flip-flops between stages. maybe 32-bit reduction use in example should still run reasonably high frequency in fpga device if going use more bits or target high frequency might want use or-tree no more 6-8 bits or:ed in each pipeline stage. can still re-use or_reduce function intermediate operations though.


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