arm - STM32 I-CODE and D-CODE buses -
stm32 documentation says i-code , d-code buses connected internal flash memory. i-code bus used fetch instructions , d-code bus used data access in code memory region (literal load).
the question why 2 separate buses used? can provide simultaneous , absolutely independent access flash memory?
as can see stm32 rm0090 reference manual (page 73), i-code , d-code busses cannot access flash memory independently, access flash interface independently:
as why there two: have separate chaches, i-code bus implements prefetch, useless data fetching. relevant part of reference manual (page 84):
data management
literal pools fetched flash memory through d-code bus during execution stage of cpu pipeline. cpu pipeline consequently stalled until requested literal pool provided. limit time lost due literal pools, accesses through ahb databus d-code have priority on accesses through ahb instruction bus i-code. if literal pools used, data cache memory can enabled setting data cache enable (dcen) bit in flash_acr register. feature works instruction cache memory, retained data size limited 8 rows of 128 bits.
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