VHDL using two components from a second file -

i have problem vhdl code, use mypackage.vhd contains components. here have added use work.mypackage.all; use necessary components part. part uses 2 components, 1 of them gives me error when try compile file. if include 2 components in same format, copy pasted components mypackage.vhd 1 , worked, once delete them use them mypackage.vhd gives me error. cant figure out problem thank in advanced helping.

in short: have 2 vhd file, mypackage.vhd,with components , second 1 (alu.vhd) uses mypackage.vhd components (use work.mypackage.all;), looks cant identify alu_1 components mypackage.vhd. dont know why.

here error:

** error (suppressible): c:/../alu_32.vhd(47): (vcom-1141) identifier "alu_1" not identify component     declaration. 

the 2 components code uses: alu_32 has no error, alu_1 has error when tries use mypackage.vhd.

component alu_1     port (         a, b, c_in, less : in std_logic;         alucontrol : in std_logic_vector (3 downto 0);         c_out, result, set : out std_logic         ); end component;  component alu_32     generic (alu_size : integer := 31); -- il suffit de chager la valeur 31 celle de la taille de lalu desiree!     port (         srca, srcb : in std_logic_vector(alu_size downto 0);         alucontrol : in std_logic_vector (3 downto 0);         c_out : out std_logic;         result : out std_logic_vector (alu_size downto 0);         0 : out std_logic         ); end component; 

my code:

library ieee;   use ieee.std_logic_1164.all;   use ieee.std_logic_arith.all;   use ieee.std_logic_unsigned.all;   use work.mypackage.all;     entity alu_32_generic generic (alu_size : integer := 31); -- il suffit de chager la valeur 31 celle de la taille de lalu desiree! port (     srca, srcb : in std_logic_vector (alu_size downto 0);     alucontrol : in std_logic_vector (3 downto 0);     c_out : out std_logic;     result : out std_logic_vector (alu_size downto 0);     0 : out std_logic     );   end alu_32_generic;   architecture alu_32 of alu_32  signal less_i : std_logic_vector (alu_size downto 0); signal result_i : std_logic_vector (alu_size downto 0); signal c_in_i : std_logic_vector (alu_size + 1 downto 0); signal set : std_logic_vector (alu_size downto 0);        begin 0 <= result_i(31) or result_i(30);  gen_reg : in alu_size downto 0 generate     alu_32 : alu_1     port map(         => srca(i),          b => srcb(i),          c_in => c_in_i(i),          alucontrol => alucontrol,          c_out => c_in_i(i + 1),          less => less_i(i),          set => set(i),          result => result_i(i)     );  end generate gen_reg;     c_in_i(0) <= alucontrol(2); c_out <= c_in_i(alu_size + 1); less_i(0) <= set(31); less_i(alu_size downto 1) <= (others => '0');  result(alu_size downto 0) <= result_i;     end alu_32; 

without identifying line 47 (your example line counts don't match) note entity alu_32_generic declaration:

  entity alu_32_generic 

the architecture entity name:

  architecture alu_32 of alu_32 

doesn't match.

after correcting entity name in architecture declaration , commenting out 3 use clauses not needed:

  -- use ieee.std_logic_arith.all;   -- use ieee.std_logic_unsigned.all;   -- use work.mypackage.all; 

your code analyzes (which vcom does).

note if enable use clause more mypackage declaration found architecture declarative item supplant 1 in package. use clause not affecting problem.

from verror:

vcom message # 1141:
syntax requires component name. name given not denote component declaration.

you note 2 usages of alu_1 in code appear valid. closest line 47 of example appears on line 40 (second line below):

gen_reg : in alu_size downto 0 generate     alu_32 : alu_1 

you note first occurrence in component declaration within architecture declaration:

  architecture alu_32 of alu_32   component alu_1     port ( 

which raises question whether or not have entity declaration alu_32 lurking around.

the moral of story here don't re-declare things don't need , entity name right in architecture declaration.