vhdl - Passing the (initial) value of a shared variable to a generic during component instantiation -

i trying structure testbench such, each test case represented record holds parameters test case, e.g. input file names, generics used dut instantiation &cetera. idea 1 assignment needs changed switch between different test cases.

type string_ptr access string; type test_case_t record       input_file : string_ptr;       ...   end record;    shared variable test_case_1 : test_case_t := (       input_file => new string'("path input file 1")     ...   );   shared variable test_case : test_case_t := test_case_1;  dut: my_module     generic map (         file_name => test_case.input_file.all     );         ... 

a string pointer used input_file since no unconstraint arrays allowed inside record type declaration (in case, pre-vhdl-2008).
due string pointer in test_case_t have use shared variable test_case_1.
however, when try simulate testbench in xilinx ise/isim 14.4 simulator keeps using default value of generic , not value pass in testbench (i assume bug).

i tried work around issue with

constant input_file : string := test_case.input_file.all;  dut: my_module     generic map (         file_name => input_file     );     ... 

this using initial value of shared variable initial value constant. however, assignment crash xilinx compiler before simulation started (another bug assume).

at point no longer trust xilinx tools @ all.
question if shared variable can used pass generic values module shown above (first code snippet)?
also, usage of shared variable advisable testbenches? have used constant or signal test_case_1 due use string_ptr type in test_case_t seems not allowed.

you can associate fixed length string expression value of generic constant actual in generic map formal of type string unbound subtype indication.

to understand why works turn elaboration of generics.

ieee std 1076-2008 (the lrm):

14.3 elaboration of block, package, or subprogram header

14.3.2 generic clause

elaboration of generic clause consists of elaboration of each of equivalent single generic declarations contained in clause, in order given. elaboration of generic declaration establishes generic can subsequently referenced.

6.5.6.2 generic clauses (para 5)

the subtype denoted generic type specified corresponding actual in generic association list. error if no such actual specified given formal generic type (either because formal generic unassociated or because actual open).

(and note actual of generic expression , association list generic map. note doesn't match brian's expectations on how subtype indication string generic determined ada background.)

so means this:

entity my_module     generic ( constant file_name: string := "default_string"); end entity;  architecture foo of my_module begin unlabeled:     process     begin         report "generic file_name = " & file_name;         wait;     end process; end architecture;  entity foo end entity;  architecture fum of foo      type string_ptr access string;     type test_case_t          record               input_file : string_ptr;           end record;       shared variable test_case_1 : test_case_t :=              (input_file => new string'("""path input file 1"""));       shared variable test_case : test_case_t := test_case_1;      component my_module         generic (             constant file_name: string := "default string"         );     end component; begin dut: my_module     generic map (         file_name => test_case.input_file.all     ); end architecture; 

is legal vhdl:

ghdl -a my_module.vhdl
ghdl -e foo
ghdl -r foo
my_module.vhdl:10:9:@0ms:(report note): generic file_name = "path input file 1"

as this:

architecture fuu of foo      -- type string_ptr access string;     -- type test_case_t     --     record     --         input_file : string_ptr;     --     end record;     -- shared variable test_case_1 : test_case_t :=     --         (input_file => new string'("""path input file 1"""));     -- shared variable test_case : test_case_t := test_case_1;      component my_module         generic (             constant file_name: string := "default string"         );     end component; begin dut: my_module     generic map (         file_name => """some other string""" -- test_case.input_file.all     ); end architecture; 

which gives:

ghdl -a my_module.vhdl
ghdl -e foo
ghdl -r foo
my_module.vhdl:10:9:@0ms:(report note): generic file_name = "some other string"

so tells couple of things.

isim not quite standard compliant in implementing generics. difference in 2 architectures can see particular isim version not determining subtype actual per 6.5.6.2 quoted above noting you're trying deal string subtype (length). (you'd expect if point out xilinx fix it).

you try not providing default expression in generic clause in entity declaration (noting component declarations should match). see 6.5.6.2 para 4:

the value of generic constant may specified corresponding actual in generic association list. if no such actual specified given formal generic constant (either because formal generic unassociated or because actual open), , if default expression specified generic, value of expression value of generic. error if no actual specified given formal generic constant , no default expression present in corresponding interface element. error if of subelements of composite formal generic constant connected , others either unconnected or unassociated.

it's either or situation, if neither it's error.

there's propagating top level constant or generic (where supported tool implementation) requires passing every unique value through generics of each successive hierarchical block element. require implementation supports 6.5.6.2 properly. (see bit 6.5.6.2 para 4 above).

and if clever , simulation , synthesis implementations supported configuration declarations there's way through configuration (providing 2 different use clauses 2 different packages providing component declarations 2 different actuals in generic clauses - requires vhdl implementation support 6.5.6.2, see para 4 above). method allow simulate different configurations different sets of actual values.