VHDL average of Array through for loop -

i have array of x integer values in vhdl declared variable inside process. calculate average of values in loop. if write out 3 values manually works fine (tested on hardware):

entity myentity port(     enable   : in std_logic ;     clk      : in std_logic;     speedout : out integer ); end myentity;  average : process   type      samplearray         array (2 downto 0) of integer;   variable  speedsamples        : samplearray;    begin   wait until rising_edge(clk);   if enable = '1'      speedout <=  ( speedsamples(0)+ speedsamples(1)+speedsamples(2) ) / 3;   end if; end process average; 

if use loop same speedout constant 0:

entity myentity port(     enable   : in std_logic ;     clk      : in std_logic;     speedout : out integer ); end myentity;  average : process   type      samplearray         array (2 downto 0) of integer;   variable  speedsamples        : samplearray;   variable  tempvar             : integer;   begin   wait until rising_edge(clk);   if enable = '1'      in 0 2 loop        tempvar := tempvar +  speedsamples(i);                 end loop;      speedout <=  tempvar / 3;   end if; end process average; 

i aware need lot of resources if array bigger think there fundamentally wrong code.

is there proven method of calculating moving average in vhdl?

it's not efficient add large number of samples each clock period that; adder n inputs consume lot of logic resource n starts increase.

my suggestion implement memory buffer samples, have many locations want samples in rolling average. have 1 new sample written each clock cycle; add same sample total on following clock edge.

using dual-port memory, can simultaneously read out 'oldest' sample in memory same location (provided have memory in read-before-write mode). subtract total, perform divide. expect far efficient divisor power of two, divide not consume logic resource. other types of divider use relatively lots of logic.

so design boil down memory buffer, 3-input adder, counter use pointer sample buffer, , wire-shift divider. if performance issue, pipeline add/subtract phases ever needed 2-input adders.

as actual coding question creating multi-input adder using loop, on top of suggestions made in comments, it's synthesis tool whether able identify multi-input adder. have looked in synthesis report messages relating segment of code?