verilog - Divide by 2 clock and corresponding reset generation -


my question using generate synthesizable divide 2 clock , corresponding reset in verilog.

we can generate divide 2 clock below using verilog

module frquency_divider_by2(   input      rst_n,   input      clk_rx,   output reg clk_tx );  @ (posedge clk_rx) begin   if (~rst_n) begin     clk_tx <= 1'b0;   end   else begin     clk_tx <= ~clk_tx;   end end  endmodule

my question how generate corresponding reset(to used flops using clk_tx) using rst_n

can 1 me same.

i appreciate help

to async apply reset , release after 2 positive edges of clk_tx. waiting 2 positive edges stops reset being low fractions of clock period. 

output reg rst2_n; reg temp;  @ (posedge clk_rx, negedge rst_n ) begin   if (~rst_n) begin     {rst2_n,temp} <= 2'b0;   end   else begin    {rst2_n,temp} <= {temp, 1'b1};   end end

for synchronous reset need check if low section of faster clock, during synthesis need check cdc (clock domain crossing).

output reg rst2_n; reg [1:0] sync_reset_n; @ (posedge clk_rx) begin   sync_reset_n[1:0] <= {sync_reset_n[0], rst_n};   rst2_n            <= &sync_reset_n ; //and bit reduction end

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