Verilog Testbench constant exp and pram compilation and simulation errors -

source code:

module singleonebit(n,t);  parameter integer w; //width or number of inputs n  input wire [w-1:0] n; output wire t;     wire[w*(w-1):0] n1; //for anding possible combinations of 2 bits  wire r; // oring tha ands. if r = 1 n contians more 1 bit value 1 wire rs; //ors bits of input. used checking if there 1 bit value 1 or 0s wire r1; // not of r;   buf(r, 0); //initialy r should 0; buf(rs, 0); //initialy rs should 0;  genvar i, j;  generate  for(i = 0; i<w; i=i+1) begin  or(rs,n[i],rs);  for(j = i+1; j<w; j=j+1) begin  and(n1[(i*w)+j], n[i], n[j]); or(r,n1[(i*w)+j],r);  end     end  endgenerate  not(r1, r); and(t,rs,r1);    endmodule  

testbench code:

`include "c:/users/muaz aljarhi/google drive/muaz/hardware_designs/verilog course/singleonebit.v"  module singleonebit_tb();  integer n = 5;  reg[n-1:0] n; wire t;  singleonebit sob(.n(n),.t(t)); defparam sob.w = n;  initial begin  $monitor("n = %b, t = %b",n,t);      end    endmodule  

compilation of verilog testbench code yeilds following errors:

** error: c:/users/muaz aljarhi/google drive/muaz/hardware_designs/verilog course/singleonebit_tb.v(7): range must bounded constant expressions. ** error: c:/users/muaz aljarhi/google drive/muaz/hardware_designs/verilog course/singleonebit_tb.v(11): right-hand side of defparam must constant.

how declare variable or constant experssion can changed within test bench? tried using parameter parameters not variables can changed. in advance

edit: have declare different instantiations of module possibly different input reg variables or there way?

i tried this:

singleonebit sob(.n(n[0]),.t(t)); defparam sob.w = 32'd5; 

but simulating, using modelsim yeilds following:

# ** error: (vopt-2293) parameter 'w' in instance ('/singleonebit_tb/sob') of ('singleonebit') declared without value, #  # , instantiation not provide value parameter. 

how avoid getting error @ simulation? again.

as parameters compile-time (technically elaboration-time) constants, cannot have them change during course of execution. thus, first error in sob.w set n not valid n cannot determined fixed value during elaboration phase (part of compiling entire design, before simulation can take place).

the second error result of declaration of singleonebit module sob not defining hte w parameter. while define later defparam, need provide default value of w. can in module changing declaration of w include default value:

parameter integer w = 32'd5; 

as seem want test various widths of module, dont see way around not declaring multiple widths of module. of course, can use generate statement produce these module of various width compactly; sure there isnt way of changing parameter in middle of simulation.

edit: forgot mention defparam construct might removed language (iee1800-2009 , ieee1800-2012 both list might eliminated in future), should avoid using allow code compatible future tools.